Cache memory architecture with on-chip tag array and off-chip data array
US6247094A · kind A · utility
81Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1997 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Dec 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an improved cache memory architecture with way prediction. The improved architecture entails placing the address tag array of a cache memory on the central processing unit core (i.e. the microprocessor chip), while the cache data array remains off the microprocessor chip. In addition, a way predictor is provided in conjunction with the improved memory cache architecture to increase the overall performance of the cache memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.