Rapid selection of oldest eligible entry in a queue
US6247114A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 1999 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Feb 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor having an instruction queue capable of out-of-order instruction dispatch and rapidly selecting one or more oldest eligible entries is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations and may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. The microprocessor may be further configured with high speed control logic coupled to the instruction queue. The control logic may comprise a number of pluralities of multiplexers, wherein the first plurality of multiplexers are configured to select a first subset of the instructions stored in the queue. The second plurality of multiplexers then select a second subset of instructions from the first subset. This process is repeated in each successive plurality of multiplexers until the oldest eligible entry is selected. A data queue and method for managing a queue are also contemplated, as is a computer system utilizing the above-mentioned micr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.