Delaying clock and data signals to force synchronous operation in digital systems that determine phase relationships between clocks with related frequencies
US6247137A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 20, 2000 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Apr 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus forces synchronous operation in a system that determines a phase-based relationship between two clocks by providing selectable delays of clock and data signals. A sending IC transmits data to the receiving IC over a data bus, and provides a strobe (clock) signal to validate data at the receiving IC. The phase relationship between the strobe signal and the internal clock of receiving IC is initially unknown. Within the receiving IC, the strobe signal is used to form four clock signals that clock data into four flip flops using a round robin scheme. Each of the round robin flip flops has a valid read window, and pair of multiplexors route the outputs of the round robin flip flops to a pair of flip flops that are clocked using internal clocks of the receiving IC. A select signal in the clock domain of the receiving IC is provided to the pair of multiplexors. The select signal can have one of two possible orientations. A phase detection circuit selects the proper orientation. Asynchronous behavior can occur if the initial timing of the select signal is close to the point at which the phase detection circuit decides whether to toggle the select signal, thereby mak…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.