John A. Wickeraad
43Patents
11h-index
22Co-inventors
75Inventor score
Filing activity: Jul 23, 1987 → Oct 30, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6490654B2 | Method and apparatus for replacing cache lines in a cache memory | Physics | 64 | Expired |
| US4789874A | Single channel encoder system | Physics | 53 | Expired |
| US6636906B1 | Apparatus and method for ensuring forward progress in coherent I/O systems | Physics | 43 | Expired |
| US6247137A | Delaying clock and data signals to force synchronous operation in digital systems that determine phase relationships between clocks with related frequencies | Physics | 25 | Expired |
| US6718454B1 | Systems and methods for prefetch operations to reduce latency associated with memory access | Physics | 22 | Expired |
| US6662313B1 | System and method for multiple cycle capture of chip state | Physics | 20 | Expired |
| US7596741B2 | Packet protection for header modification | Electricity | 20 | Active |
| US5944843A | Method and apparatus for using the unused bits of a data packet to transmit additional information | Electricity | 15 | Expired |
| US7346812B1 | Apparatus and method for implementing programmable levels of error severity | Physics | 14 | Expired |
| US7325164B2 | System and method for multiple cycle capture of chip state | Physics | 11 | Expired |
| US6647469B1 | Using read current transactions for improved performance in directory-based coherent I/O systems | Physics | 11 | Expired |
| US6928525B1 | Per cache line semaphore for cache access arbitration | Physics | 10 | Expired |
| US7594158B2 | Parity error checking and compare using shared logic circuitry in a ternary content addressable memory | Physics | 7 | Active |
| US6591332B1 | Apparatus and method for tracking flushes of cache entries in a data processing system | Physics | 6 | Expired |
| US7221126B1 | Apparatus and method to align clocks for repeatable system testing | Physics | 6 | Expired |
| US7757152B2 | Data corruption scrubbing for content addressable memory and ternary content addressable memory | Physics | 6 | Active |
| US6775640B1 | Performance adder for tracking occurrence of events within a circuit | Physics | 6 | Expired |
| US7624313B2 | TCAM BIST with redundancy | Physics | 4 | Active |
| US7852653B2 | Content addressable memory | Physics | 4 | Active |
| US8627448B2 | Selective invalidation of packet filtering results | Electricity | 4 | Active |
| US7602629B2 | Content addressable memory | Physics | 3 | Active |
| US7571371B2 | Parallel parity checking for content addressable memory and ternary content addressable memory | Physics | 3 | Active |
| US8327031B2 | Support chip for handling network chips on a network device | Electricity | 3 | Active |
| US8245109B2 | Error checking and correction (ECC) system and method | Physics | 2 | Active |
| US8473832B2 | Parity error checking and compare using shared logic circuitry in a ternary content addressable memory | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.