Trench flash memory with nitride spacers for electron trapping
US6249022A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1999 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Oct 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A method for fabricating a flash memory cell is described. A conformal ultra thin oxide layer is formed on a substrate having a trench formed therein, followed by forming silicon nitride spacers on the portion of the ultra thin oxide layer which covers the sidewalls of the trench. The silicon nitride spacers are separated into a first silicon nitride spacer on the right sidewall and a second silicon nitride spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the silicon nitride spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.