Bottom side C4 bumps for integrated circuits
US6249136A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a test configuration for an integrated circuit employing a controlled, collapse chip connection technology to attach to another substrate is disclosed. The method includes the steps of forming one or more vias in a semiconductor substrate corresponding to the integrated circuit and forming circuitry on a top surface of the semiconductor substrate. The method further includes filling the one or more vias with a conductive material to form conductive channels through the semiconductor substrate which selectively couples to the circuitry to provide control signals thereto and receive output signals therefrom. One or more bond pads are formed on a bottom surface of the semiconductor substrate and correspond to the one or more conductive channels. The one or more bond pads on the bottom surface of the semiconductor substrate are coupled to bond pads on the another substrate using the controlled, collapse chip connection technique, which allows the top surface of the semiconductor substrate to be accessible for design verification or circuit test processes. The present invention further includes a controlled, collapse connection chip carrier system which includes a ba…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.