Method, circuit and/or architecture for reducing gate oxide stress in low-voltage regulated devices
US6249177A · kind A · utility
5Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2000 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Sep 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit, a second circuit and a switch. The first circuit may be configured to receive a first supply voltage and may be coupled to a first ground. The second circuit may be configured to receive a second supply voltage and may be coupled to a second ground. The second circuit may be disabled in response to a control signal. The first and second supply voltages may be controlled by a reference voltage. The switch may be coupled between the first and second circuits and may be configured to connect the first and second circuits when the second circuit is disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.