Derrick J. Savage
6Patents
1h-index
8Co-inventors
44Inventor score
Filing activity: Jun 26, 1998 → Jul 10, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6249177A | Method, circuit and/or architecture for reducing gate oxide stress in low-voltage regulated devices | Electricity | 5 | Expired |
| US6292013A | Column redundancy scheme for bus-matching fifos | Physics | 1 | Expired |
| US6055177A | Memory cell | Physics | 1 | Expired |
| US9596091B2 | Multiple sensor data processor interface and relay | Electricity | 1 | Active |
| US11792264B2 | Multiple sensor data processor interface and relay | Electricity | 0 | Active |
| US10250690B2 | Multiple sensor data processor interface and relay | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.