Redundancy programming using addressable scan paths to reduce the number of required fuses
US6249465A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are disclosed which provide the capability of repairing an optimum number of defective memory segments, such as RAM segments, in order to minimize the amount of unused repairing circuitry, such as fuses used for repairing defects within the memory. A preferred embodiment of the present invention provides a RAM block implemented such that the number of fuses required for repairing defects therein is proportional to the optimum number of defective segments capable of being repaired. A preferred embodiment allows for repairing an optimum number of defective segments, while being capable of repairing any of the segments (up to the optimum number) by mapping repair data to an appropriate defective segment. A preferred embodiment provides a repairable RAM block comprising multiple segments of RAM memory cells that are each repairable, a state machine capable of generating repair data for repairing one or more defective segments, a scan address machine capable of generating data identifying one or more defective segments, and a mapping circuitry for mapping the generated repair data of the state machine to the one or more defective segments specified by the scan addres…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.