System for expanding PCI bus loading capacity
US6249834A · kind A · utility
14Cited by
295References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1997 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Oct 1, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for expanding the loading capacity of a PCI bus in an information processing system having a multiple bus architecture. In one embodiment, the system comprises a processor-to-PCI bridge connected to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. A plurality of add-in board connectors are coupled to each of the generated PCI buses. In another embodiment, the system comprises two or more processor-to-PCI bridges connected to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. The resulting system expands the loading capacity of a PCI bus while adding resistance to single point failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.