Multi-bank ESDRAM with cross-coupled SRAM cache registers
US6249840A · kind A · utility
6Cited by
7References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 23, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Oct 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-bank ESDRAM, and an associated method, provides for the caching of data accessed from any DRAM memory array of the multi-bank ESDRAM device to any SRAM cache register of the ESDRAM device. Execution of a read operation is carried out using an existing command set utilized to read data from conventional ESDRAM devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.