Method of making select gate self-aligned to floating for split gate flash memory structure
US6251727A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 1998 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Nov 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A process for making self-aligned split-gate non-volatile memory cell is disclosed. It includes the step of using a nitride photomask in conjunction with a photoresist to etch the nitride layer and cause it to become a stepped nitride layer having a high thickness region and a low thickness. Then a poly-1 photomask is used in conjunction with a photoresist to etch through a first portion of the low thickness region to expose an underlying poly-1 layer intended to be floating gate, wherein at the same time, a portion of the high thickness region adjacent to the first portion of the low thickness region is also etched to a reduced thickness. After poly-1 oxidation, a cell drain photomask is used in conjunction with a photoresist to etch through a second portion of the low thickness region using a nitride etch and an underlying poly-1 layer using a poly etch. The portion of the high thickness region adjacent to the second portion of the low thickness region is also etched to a reduced thickness during the nitride etch. With such a stepped nitride layer approach, the floating gate and cell drain are formed using the same nitride photomask, thus ensuring the self-alignment of the select…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.