Method and apparatus for forming self-aligned code structures for semi conductor devices
US6251732A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Aug 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/383
Abstract
Improved methods for forming integrated circuit devices with alignment structures such as a read-only memory (ROM) array in preparation for code programming with a mask is disclosed. In one embodiment, a gate oxide layer is deposited over a substrate and a gate stack layer is formed over the gate oxide layer. The gate stack layer includes a conductive layer and a sacrificial gate layer formed above the conductive layer with a thin layer of etch stop material in between. The gate stack layer is patterned and etched to form a plurality of wordlines having openings therebetween. An ion barrier layer is deposited over the patterned gate stacks, filling the openings. The ion barrier layer is then etched back to form alignment structures in the openings. A code programming mask, is deposited over the resulting structure and patterned to expose portions of the sacrificial gates. The exposed portions of the plurality of sacrificial gates are removed, followed by ion implantation in the designated channel regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.