Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices
US6251747A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Nov 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a shallow trench isolation region protects the corner oxide from being etched during processing. Oxide recessing in the trench is undesirable since it results in high electric fields around the sharp top corners of the trenches and V.sub.t roll-off of the transistors. According to one example embodiment, STI regions filled with an HDP oxide and having undergone planarization, are masked. The masking substantially covers the HDP oxide and overlaps at least portions of nitride regions. Unmasked areas of the nitride regions are etched away forming nitride spacers on both sides of the HDP oxide fill.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.