Process for polycrystalline silicon gates and high-K dielectric compatibility
US6251761A · kind A · utility
49Cited by
3References
19Claims
0Family size
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Key dates
| Filing date | Nov 22, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Nov 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate stack (104) including a gate dielectric with reduced effective electrical thickness. A high-k dielectric (108) is formed over the silicon substrate (102). Remote plasma nitridation of the high-k dielectric is performed to create a nitride layer (107) over the high-k dielectric (107). A conductive layer (110) is formed over the nitride layer (107) forming the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.