Semiconductor memory device
US6252269A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Oct 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/211
Abstract
According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.