Semiconductor device, and method of fabricating the same
US6252272A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Mar 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A surface portion of a semiconductor substrate 41 is serrated at intervals equal to a minimum processing size to form impurity diffusion layers in peaks. These impurity diffusion layers are isolated from each other by valleys. At a valley where a gate is formed, the gate and impurity diffusion layers and in peaks on the two sides of the gate form a MOS transistor. A valley in which no gate is formed functions as an element isolation region. Since a MOS transistor or an element isolation region is formed in one valley, the element area is reduced. A surface of a p-type semiconductor substrate is serrated to form n.sup.+ -type impurity regions in peaks and floating gates having an upper spired portion in valleys via a silicon oxide film. Control gates are formed on the floating gates via a tunnel oxide film. The lower portion of the control gate has a shape corresponding to the valley and opposes the upper portion of the floating gate by self-alignment. Data is written or erased by using a tunnel current flowing of electrons through the tunnel oxide film between the floating gate and control gate having the above-mentioned shapes and positional relationship. This achieves micropatter…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.