Clock distribution circuit in an integrated circuit
US6252449A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1998 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Dec 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an integrated circuit including at least one logic circuit, able to operate at a first operating frequency, and a clock distribution circuit, the clock distribution circuit receiving a first clock signal and providing to the logic circuit a second clock signal, generated from the first clock signal, the frequency of the second clock signal being substantially equal to the first operating frequency. The clock distribution circuit includes a frequency multiplying circuit for generating the second clock signal, so that the frequency of the first clock signal may be lower than the first operating frequency to reduce or minimize the power consumed by the clock distribution circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.