Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse
US6252798A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1998 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Jun 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device comprises a memory cell array having plural electrically erasable memory cells including a gate, a source, a drain, and an electric charge accumulation layer each disposed in a matrix form. A data writing section writes data into memory cells in this memory cell array. A data reading section reads out data in memory cells of the memory cell array. A data erasing section erases data in memory cells of the memory cell array. A control section controls, when applying a first signal to the gate in a specified memory inhibited of writing and applying a second signal to a node capacitively coupled to at least one of source and drain, in writing data into the memory cells, so that the second signal may fall later than the first signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.