Process for restricting interdiffusion in a semiconductor device with composite Si/SiGe gate
US6255149A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1999 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Oct 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method which includes, prior to depositing the encapsulating silicon layer: A) depositing on the Si.sub.1-x Ge.sub.x layer a thin film of amorphous or polycrystalline silicon, then in treating said silicon film with gas nitric oxide at a temperature between 450 to 600.degree. C. and at a pressure level of 10.sup.4 to 10.sup.5 Pa to obtain a thin nitrided silicon film; or B) depositing on the Si.sub.1-x Ge.sub.x layer a thin film of amorphous or polycrystalline silicon and oxidizing the silicon film to form a surface film of silicon oxide less than 1 nm thick and optionally treating the oxidized amorphous or polycrystalline silicon film with nitric oxide as in A). The invention is applicable to CMOS semiconductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.