Flash memory and method for fabricating the same
US6255170A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Apr 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A memory device and a method for manufacturing the same is provided that reduces a resistance of the source region and reduces an effective cell size. The memory includes tunnel insulating films and floating gates formed stacked on a plurality of prescribed regions of a semiconductor substrate, a plurality of stacked gate insulating films, control gate lines and gate cap insulating films extend in a first direction with a zigzag pattern to cover the floating gates. Thus, the distance between adjacent control gate lines varies. Source regions are formed in the semiconductor substrate where a narrow space exists between the control gate lines stacked on the floating gates, and drain regions are formed in the semiconductor substrate where a wider space exists between the control gate lines stacked on the floating gates. Source contact regions are formed to expose the source regions, and a first conductive plate is coupled to the source regions. Bit line contact regions are formed to expose the drain regions. A second conductive line is formed in a direction crossing the control gate lines at a right angle coupled to the drain regions. The contact regions are formed in a zigzag pattern…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.