Method of fabricating self-aligning stacked capacitor using electroplating method
US6255187A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Apr 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/696
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a self-aligned stacked capacitor is provided, in which buried contacts and storage nodes are simultaneously formed by electroplating. In this method, a semiconductor substrate having exposed conductive areas is prepared for, and an interlayer insulative layer having buried contact holes that expose the conductive areas, is formed over the semiconductor substrate. A lower conductive seed layer is then formed over the entire surface of the innerwalls of the buried contact holes and the upper surface of the interlayer insulative layer. Non-conductor patterns having storage node holes that expose the buried contact holes, are then formed over the lower conductive seed layer on the upper surface of the interlayer insulative layer. A buried contact that fills the buried contact hole, and a lower electrode that fills the storage node hole, are then simultaneously formed by electroplating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.