Technique for low-temperature formation of excellent silicided .alpha.-Si gate structures
US6255203A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1998 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Dec 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This application relates to a process to suppress the impurity diffusion through gate oxide on silicided amorphous-Si gate structures that utilize the silicide layers as the implantation barrier to minimize the impurity diffusion by reducing the projectile range and implant-induced defects, resulting in smaller flat-band voltage(V.sub.FB) shift and better characteristics of the breakdown field(E.sub.bd) and charge to breakdown(Q.sub.bd). In addition, the amorphous-Si underlying layer is simultaneously kept during the formation of a low-temperature self-aligned silicide (SAD) process to further retard the impurity diffusion. Hence, the usage of such bilayered silicide/amorphous-Si films could effectively retard the impurity diffusion, by combining both effects of the amorphous-Si layer and the silicide process or inducing other undesirable effects such as the increase of gate sheet resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.