Flash memory structure and method of manufacture
US6255689A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 1999 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Dec 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6893
Abstract
A flash memory cell structure and its method of manufacture. The flash memory cell has a vertical configuration. An opening and then a trench are formed in a substrate by etching. The trench (defined as the recessed section of the substrate) is used for forming a shallow trench isolation structure. The substrate region between two neighboring openings (defined as the protruding section of the substrate) is used for forming a common drain and a channel. A source terminal is formed in the substrate at the upper comer next to the shallow trench structure. A tunnel oxide layer is formed over the substrate surface of the opening. A floating gate and a dielectric layer are formed over the tunnel oxide layer. A control gate is formed inside the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.