3-D smart power IC
US6255710A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1998 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | May 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
An integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a source positioned adjacent the upper surface of the substrate, a control terminal between the upper and lower surfaces, and a drain positioned adjacent the lower surface of the substrate. A high resistance layer is formed on a portion of the upper surface of the substrate, either directly overlying or adjacent to the power device, and doped semiconductor material is positioned on the high resistance layer. Control circuitry is formed in the doped semiconductor material. The high resistance layer can be conveniently formed by growing a layer of AlAs and growing doped layers on the AlAs. The AlAs can be easily oxidized thereafter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.