Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines
US6256242A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | May 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A margin test on a Dynamic Random Access Memory (DRAM) in accordance with the invention begins with a supply voltage level being stored in all memory cells of the DRAM. Circuitry incorporated into each sense amplifier of the DRAM then isolates the digit line equilibrating circuitry in each sense amplifier from the cell plate voltage DVC2 or supply voltage V.sub.CC to which the equilibrating circuitry is normally connected and connects the equilibrating circuitry to ground instead. The equilibrating circuitry is then activated for a predetermined refresh interval of about 150 to 200 milliseconds to equilibrate the true and complementary digit lines in each digit line pair of the DRAM to ground for the refresh interval. This stresses all the memory cells in the DRAM with a V.sub.CC -to-ground voltage drop for the entire refresh interval. The DRAM is then restored to normal operations and all the memory cells in the DRAM are read to identify any that leaked too much charge during the refresh interval, which identifies any memory cells that failed the margin test and require repair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.