Memory device with support for unaligned access
US6256253A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.