Shared datapath processor utilizing stack-based and register-based storage spaces
US6256725A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1998 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Dec 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is configured to include at least two architecturally-distinct storage spaces, such as, for example, a stack for storing control operands associated with one or more instructions, and a register file for storing computational operands associated with one or more instructions. The processor further includes a datapath which is at least partially shared by the stack and register file, a multiplexer operative to select an output of either the stack or the register file for application to an input of the shared datapath, and a demultiplexer operative to select an output of the shared datapath for application to an input of either the stack or the register file. A program executed by the processor selects one of the storage spaces using, for example, a tag bit associated with a given instruction and indicating which of the storage spaces is to be used with that instruction, or a branch machine view (bmv) instruction which generates a control signal operative to select the given one of the storage spaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.