C. John Glossner
41Patents
12h-index
21Co-inventors
77Inventor score
Filing activity: Mar 31, 1998 → May 16, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6842848B2 | Method and apparatus for token triggered multithreading | Physics | 44 | Expired |
| US7251737B2 | Convergence device with dynamic program throttling that replaces noncritical programs with alternate capacity programs based on power indicator | Emerging Cross-Sectional Technologies | 29 | Expired |
| US6904511B2 | Method and apparatus for register file port reduction in a multithreaded processor | Physics | 28 | Expired |
| US7593978B2 | Processor reduction unit for accumulation of multiple operands with or without saturation | Physics | 27 | Active |
| US6260189A | Compiler-controlled dynamic instruction dispatch in pipelined processors | Physics | 26 | Expired |
| US6990557B2 | Method and apparatus for multithreaded cache with cache eviction based on thread identifier | Physics | 21 | Expired |
| US6925643B2 | Method and apparatus for thread-based memory access in a multithreaded processor | Emerging Cross-Sectional Technologies | 15 | Expired |
| US6968445B2 | Multithreaded processor with efficient processing for convergence device applications | Physics | 14 | Expired |
| US6282585A | Cooperative interconnection for reducing port pressure in clustered microprocessors | Physics | 14 | Expired |
| US6230251A | File replication methods and apparatus for reducing port pressure in a clustered processor | Physics | 13 | Expired |
| US7475222B2 | Multi-threaded processor having compound instruction and operation formats | Physics | 13 | Expired |
| US6079010A | Multiple machine view execution in a computer system | Physics | 13 | Expired |
| US8074051B2 | Multithreaded processor with multiple concurrent pipelines per thread | Physics | 12 | Expired |
| US7797363B2 | Processor having parallel vector multiply and reduce operations with sequential semantics | Physics | 12 | Active |
| US6256725A | Shared datapath processor utilizing stack-based and register-based storage spaces | Physics | 11 | Expired |
| US6912623B2 | Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy | Emerging Cross-Sectional Technologies | 10 | Expired |
| US7428567B2 | Arithmetic unit for addition or subtraction with preliminary saturation detection | Physics | 10 | Active |
| US10339095B2 | Vector processor configured to operate on variable length vectors using digital signal processing instructions | Physics | 9 | Active |
| US6317821A | Virtual single-cycle execution in pipelined processors | Physics | 9 | Expired |
| US6269437A | Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor | Physics | 7 | Expired |
| US9959246B2 | Vector processor configured to operate on variable length vectors using implicitly typed instructions | Physics | 5 | Active |
| US10169039B2 | Computer processor that implements pre-translation of virtual addresses | Physics | 5 | Active |
| US7349938B2 | Arithmetic circuit with balanced logic levels for low-power operation | Physics | 4 | Expired |
| US9910824B2 | Vector processor configured to operate on variable length vectors using instructions to combine and split vectors | Physics | 3 | Active |
| US6859871B1 | Method and apparatus for reducing power consumption in a pipelined processor | Physics | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.