Method of interconnecting electronic components using a plurality of conductive studs
US6258625A · kind A · utility
201Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | May 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10378
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of interconnecting electronic components by using a plurality of conductive studs on a surface of a first electronic component and a plurality of corresponding conductive vias on the surface of a second electronic component. Camber on the surface of electronic components may be overcome by coating the surface with a dielectric, planarizing the dielectric, and forming conductive vias corresponding to the contact pads thereon. The conductive studs are substantially lead-free and preferably comprise of copper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.