Memory cell configuration and corresponding fabrication method

US6258658A · kind A · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thomas Böhm · Zorneding, DE
• Volker Weinrich · Paris, FR
• Manfred Hain · Vaterstetten, DE
• Armin Kohlhase · Neubiberg, DE
• Yoichi Otani · Radeberg, DE
• Andreas Rusch · Dresden, DE
• Till Schlosser · Dresden, DE

Key dates

• Filing date: Feb 12, 1999
• Grant date: Jul 10, 2001
• Expiry date: Feb 12, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/31

Abstract

The memory cell configuration has a multiplicity of preferably ferroelectric memory cells in a semiconductor substrate. Mutually parallel bit line trenches run in the longitudinal direction in the main surface of the semiconductor substrate. Bit lines are disposed in the bottoms of the trenches. Source/drain regions are formed in the crowns of the trenches. Channel regions are provided in the walls of the trenches. The channel region on a wall in each case is configured such that a drivable selection transistor of the relevant memory cell is formed there, while the channel region on the other wall is configured such that the transistor located there is closed. Insulated word lines for driving the selection transistors run in the transverse direction along the main surface of the semiconductor substrate through the bit line trenches. Insulation trenches for insulating the source/drain regions in the longitudinal direction of neighboring memory cells run in the transverse direction in the main surface of the semiconductor substrate. A respective, preferably ferroelectric, capacitor is connected to the source/drain region of the respective memory cell and is arranged above the word li…