Sacrificial silicon sidewall for damascene gate formation
US6258679A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Dec 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating MOSFET devices in which the gate polysilicon is not consumed during damascene etch back, comprising: (a) forming a gate stack on a surface of a silicon-containing substrate, said gate stack having at least a pad oxide layer formed on said surface of said silicon-containing substrate and a nitride layer formed on said pad oxide layer; (b) forming a trough in said gate stack stopping on said pad oxide layer exposing a portion of said pad oxide layer, said trough having vertical sidewalls; (c) forming a conformal silicon layer on said gate stack and in said trough, including said vertical sidewalls and said exposed pad oxide layer; (d) removing the conformal silicon layer from said gate stack and said exposed pad oxide layer whereby silicon remains on the vertical sidewalls of said trough; (e) removing the exposed pad oxide from said trough exposing a portion of the silicon-containing substrate; (f) oxidizing the silicon on said vertical sidewalls of the trough and in said exposed silicon-containing substrate forming oxide layers in said vertical sidewalls and on said exposed silicon-containing substrate; (g) forming doped polysilicon in said trough; (h) perfor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.