Dislocation suppression by carbon incorporation
US6258695A · kind A · utility
28Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76237
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing the formation of silicon crystal defects due to extrinsic stresses in an integrated circuit chip. The source of such extrinsic stresses may be filling trenches with polycrystalline silicon or oxide, silicides, forming silicon nitride spacers or liners, or during oxide birds-beak formation, or at numerous other processing points. At an appropriate point, as each sensitive feature is defined or formed, carbon co-implanted into the silicon wafer at or near the feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.