Sacrificial deposit to improve damascene pattern planarization in semiconductor wafers
US6258711A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Apr 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing dishing and erosion of surfaces of inlaid material on semiconductor wafers. The method includes forming a sacrificial deposit or layer over at least down features of the patterned surface of the fill layer, that has a lower rate of removal during chemical-mechanical polishing than the fill layer. Elevated caps of sacrificial deposit are formed over inlaid fill material prior to pattern clearing. In CMP pattern clearing, the caps are removed and polishing proceeds at a faster rate on the slightly elevated inlaid fill upper surfaces until they are coplanar with surrounding patterned substrate. Chemical-mechanical polishing can be carried out in a single step, or in multiple steps, to produce the desired result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.