Method to produce high quality metal fill in deep submicron vias and lines
US6258717A · kind A · utility
3Cited by
11References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24917
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for plating metal in submicron structures. A seedlayer is deposited on surfaces of submicron structures. The seedlayer is annealed at a temperature of about 80.degree. C. to about 130.degree. C. Metal is plated on the seedlayer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.