Method of forming metal lands at the M0 level with a non selective chemistry
US6258727A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Jul 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/37
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The starting structure consists of a silicon substrate having diffused regions formed therein and gate conductor stacks formed thereupon that is passivated by a TEOS layer as standard. At a further stage of the wafer fabrication process, contact holes exposing some diffused regions and top of gate conductor stacks have been formed. At least one contact hole exposing a diffused region has been filled with doped polysilicon and the structure has been coated with a layer of an anti-reflective material (ARC) then, with a patterned mask to expose the ARC layer at the contact holes locations. The process improvement essentially consists in the use of a non selective chemistry which etches the doped polysilicon, the ARC and TEOS materials at substantially the same rate in a RIE etcher. A NF3/CHF3 gas mixture with a 23/77 ratio is adequate in that respect. The etch time duration is controlled first by an optical etch end-point detection system adapted to detect the signal transition at the TEOS layer exposure and then by an interferometric etch endpoint detection system to monitor the etched thickness to accurately stop when the selected depth for the M0 land recesses is reached. Finally, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.