Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency
US6260117A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1998 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Jan 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The multi-processor system according to the present invention includes at least two processors, a system bus providing communication between the processors, and a bus arbiter generating system responses to commands on the system bus. One of the processors generates a snoop response to a snooped command based on the system response to a command, associated with the same real address as the snooped command, which issued from the processor. In response to a command requesting invalidation of a cache line, a cache within the processor conditionally casts back the cache line to a transition cache in the processor. Based on the system response to the invalidation command, the transition cache either discards the cast back or converts the cast back into a command for writing the cache line in the main memory of the system. The processor also converts an exclusive read command requiring a reservation to a non-exclusive read command if that reservation has been lost prior to placing the command on the system bus. Furthermore, the transition cache in the processor may shift the memory coherency image state for a non-exclusive command, which is waiting for data to return, if a command associa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.