Compiler-controlled dynamic instruction dispatch in pipelined processors
US6260189A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1998 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Sep 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4451
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides techniques for improving the performance of pipelined processors by eliminating unnecessary stalling of instructions. In an illustrative embodiment, a compiler is used to identify pipeline dependencies in a given set of instructions. The compiler then groups the set of instructions into a code block having a field which indicates the types of pipeline dependencies, if any, in the set of instructions. The field may indicate the types of pipeline dependencies by specifying which of a predetermined set of hazards arise in the plurality of instructions when executed on a given pipelined processor. For example, the field may indicate whether the code block includes any Read After Write (RAW) hazards, Write After Write (WAW) hazards or Write After Read (WAR) hazards. The code block may include one or more dynamic scheduling instructions, with each of the dynamic scheduling instructions including a set of instructions for execution in a multi-issue processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.