Chip carrier substrate
US6262376A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1999 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Aug 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip carrier substrate including a lower layer and at least one upper layer of copper conductors on a base, a plurality of aluminum studs formed by anodization to be of substantially identical height which interconnect the layers of conductors, a layer of barrier metal electrically connecting the aluminum studs and the copper conductors to prevent direct contact therebetween, the aluminum studs and at least the upper layer of copper conductor being surrounded by a polymeric dielectric material, and a layer of adhesion/barrier metal beneath the upper copper conductor layer, between the upper copper conductor layer and the dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.