Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate
US6262453A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 1998 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Apr 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
This invention discloses a DMOS power device supported on a substrate. The DOS power device includes a drain of a first conductivity type disposed at a bottom surface of the substrate. The DMOS power device further includes a gate disposed in a trench opened from a top surface of the substrate, the gate having a polysilicon layer filling the trenches padded by a double gate-oxide structure. The double gate-oxide structure includes a thick-oxide-layer covering walls of the trench below an upper portion of the trench and a thin-gate-oxide covering walls of the upper portion of the trench thus defining a champagne-glass shaped gate in the trench. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate surrounding a top portion of the trench. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate surrounding the trench and encompassing the source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.