Method and apparatus for creating a voltage threshold in a FET

US6262461A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Daniel S. Marshall · Chandler, US
• William J. Ooms · Chandler, US
• Jerald A. Hallmark · Gilbert, US
• Yang Wang · Chandler, US

Key dates

• Filing date: Jun 22, 1998
• Grant date: Jul 17, 2001
• Expiry date: Jun 22, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.