Semiconductor memory module having double-sided memory chip layout
US6262488A · kind A · utility
53Cited by
6References
10Claims
0Family size
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Key dates
| Filing date | Apr 16, 1999 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Apr 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1572
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.