Parallel test circuit and method for wide input/output DRAM
US6262928A · kind A · utility
7Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2000 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Sep 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a parallel test circuit and method for testing even bit line and odd bit line in a memory block simultaneously. The parallel test circuit comprises an even test circuit for testing an even bit line and an odd test circuit for testing an odd bit line. The parallel test circuit also includes a write circuit for writing data to a bit line, a read circuit including a data sense amp, an output buffer, and a comparator. Furthermore, the present invention provides the capability to conduct disturbance test in neighboring even and odd cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.