Patent · US Expired

Random access memory having independent read port and write port and process for writing to and reading from the same

US6262936A · kind A · utility

14Cited by
8References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 27, 1999
Grant dateJul 17, 2001
Priority date
Expiry dateJan 27, 2019

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C8/16
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A random access memory with a read port, a write port, a read/write control signal configured to control data transfer operations at the read port and/or the write port on both rising and falling transitions, and a first random access memory array configured to store and/or retrieve data at a first random address in the first random access memory array defined by one or more signals on a write address bus and/or a read address bus. One preferred embodiment further includes a write data register storing or latching data in response to a first transition of the read/write control signal, and the array storing data in response to a second transition of the read/write control signal. Other preferred embodiments further include an n.multidot.m-bits-wide input data bus coupling a set of data inputs to the write data register, and/or an n.multidot.m-bits-wide output data bus coupling the read data register to a set of data outputs, where n and m are each independently an integer >2.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.