Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system
US6263404A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1997 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Nov 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cache sequencer circuit manages the operation of a memory cache and cache buffer so as to efficiently forward memory contents being delivered to the memory cache via the cache buffer, to a multithreading processor awaiting return of those memory contents. The sequencer circuit predicts the location of the memory contents that the processor is awaiting, and speculatively forwards memory contents from either the cache buffer or memory cache, while simultaneously verifying that the speculatively forwarded memory contents were correctly forwarded. If the memory contents were incorrectly forwarded, the sequencer circuit issues a signal to the processor receiving the speculatively forwarded memory contents to ignore the forwarded memory contents. This speculative forwarding process may be performed, for example, when a memory access request is received from the processor, or whenever memory contents are delivered to the cache buffer after a cache miss. The sequencer circuit includes a plurality of sequencers, each storing information for managing the return of data in response to one of the potentially multiple misses and resulting cache linefills which can be generated by the m…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.