Wafer sawing/grinding process
US6264535A · kind A · utility
6Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1999 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Sep 23, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49798
- WIPO fieldOther special machines
- WIPO sectorMechanical engineering
Abstract
A wafer sawing/grinding process capable of removing cracks and chipping resulted from a wafer sawing operation. A silicon wafer having an active surface and a back surface is provided. A first tape is attached to the back surface of the wafer and then the wafer is sawn along kerfs between neighboring silicon chips. A second tape is attached to the active surface of the silicon wafer before removing the first tape. The back surface of the wafer is then ground until the wafer reaches a desired thickness. A third tape is attached to the ground back surface of the wafer before removing the second tape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.