Selective seed and plate using permanent resist
US6264851A · kind A · utility
9Cited by
25References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1998 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Mar 17, 2018 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC23F1/02
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention is for a method wherein a printed circuit board can be fabricated in an electroless process with a minimum number of manufacturing steps using mild etchant conditions on an intermediary seed layer to produce low-defect, fine conductive line printed circuit boards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.