Method of forming a two transistor flash EPROM cell
US6265266A · kind A · utility
25Cited by
11References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1996 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Sep 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.