Method for forming self-aligned contacts using a hard mask
US6265296A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making self-aligned contacts on a semiconductor substrate using a hard mask. After the transistor is formed, a blanket insulating layer is formed on said semiconductor substrate. A hard mask having openings on the blanket insulating layer is formed over the insulating layer. The openings overlay the source/drain region and part of the gate electrode structure. Using the patterned hard mask, the insulating layer is etched to the gate electrode protecting layer. Then self-aligned contacts is completed by etching the insulating layer to expose the source/drain regions using the gate electrode protecting layer and the insulating sidewall spacers as the mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.