Method and material for integration of fuorine-containing low-k dielectrics
US6265779A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1998 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Aug 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Metal and insulator interconnect structures are described incorporating one or more layers of fluorinated dielectric insulation, one or more conductive wiring levels interconnected by vias and capping and/or liner materials to physically isolate the wiring levels and vias from the fluorinated dielectric such as fluorinated diamond like carbon which has a low dielectric constant. The invention overcomes the problem that can arise when fluorine in the fluorinated dielectric insulation reacts with other materials in the interconnect structure to produce unwanted fluorine-containing compounds that can interfere with the structure's mechanical integrity or interconnect function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.